1. Field of the Invention
The present invention is related to the field of semiconductor devices. More specifically it is related to tunnel field effect transistors (TFET) wherein the tunneling effect is band-to-band tunneling.
The invention further relates to a method of fabricating a semiconductor device, more particularly to a method for fabrication of tunnel field effect transistors (TFETs). More specifically the fabrication method relates to but is not limited to standard planar technology, double gate technology, finFET technology and nanotechnology, wherein the latter includes implementations with integrated nanowires.
2. Description of the Related Technology
Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) is one of the core elements of such integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
One of the problems due to the scaling down of CMOS transistors is that the power consumption keeps increasing. This is partly because leakage currents are increasing (e.g. due to short channel effects) and partly because it becomes difficult to decrease the supply voltage. The latter is mainly due to the fact that the subthreshold slope is limited to minimally about 60 mV/decade, such that switching the transistor from ON to OFF needs a certain voltage variation and therefore a minimum supply voltage.
Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), because of their absence of short-channel effects and because of their resulting low off-currents. Another advantage of TFETs is that the subthreshold slope can be less than 60 mV/dec, the physical limit of conventional MOSFETs, such that potentially lower supply voltages can be used. However, TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. The low on-currents result in long gate delays (gate delay τgate=Cgate*Vdd/Ids, with Cgate the gate capacitance, Vdd the supply voltage, and Ids the on-current) and correspondingly slow switching speed. TFETs are also ambipolar, which means that they are turned on for both high positive and high negative gate voltages. This ambipolar behavior can result in an unwanted increase of the off-current.
In US 2005/0274992, a method of fabricating an improved TFET using nanowires is disclosed. The method comprises forming in a nanotube (i.e. a nanowire without axial opening) an n-doped region and a p-doped region that are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer is deposited on the channel region of the transistor. The proposed structure still has the disadvantage of strong ambipolar behavior.
To increase the on-current of a silicon TFET, suggestions have been made in literature by Bhuwalka et al. (IEEE transactions on electron devices Vol. 52, No 7, July 2005) to add a small (about 3 nm wide) section of highly-doped Si1-xGex at the tunnel barrier. The Si1-xGex has a smaller band gap than Si such that the effective tunnel barrier width decreases due to the presence of this section. However, these structures with the Si1-xGex section can still not compete with conventional MOSFETs because of their low on-currents.
Appenzeller et al., in “Comparing Carbon Nanotube Transistors—The Ideal Choice: A Novel Tunneling Device Design” (IEEE Trans. Electron Devices, Vol. 52, pp 2568-2576 (2005)), describes a carbon nanotube based TFET, however this proposed structure still has the disadvantage of strong ambipolar behavior.
Wang et al., in “Complementary tunneling transistor for low power application” (Solid-State Electronics Vol 48, pp 2281-2286 (2004)), describes the fabrication of complementary TFETs and illustrates the low power consumption of the complementary silicon TFETs. To reduce the ambipolar behavior of the TFET, the pTFET (nTFET) has a lower p-type (n-type) doping level for the drain contact than the n-type (p-type) doping level for the source contact. This implementation has the disadvantage of an increased number of processing steps for fabrication of such devices due to the different doping levels for pTFET and nTFET. The on-current of the silicon TFETs is, furthermore, not yet comparable with the on-current of the MOSFET.
As a conclusion, there is still a need for an improved TFET design.